Integrated circuit (IC) technologies are continually progressing to smaller feature sizes, for example, down to 65 nanometers, 45 nanometers, and below. Various patterned resist layers are used to transfer a designed pattern to a wafer to form a desired IC device. For example, various resist layers are used to form multiple material layers of the wafer that combine to form a complementary metal-oxide-semiconductor device. During wafer processing, complete removal of each resist layer from the wafer is desired since resist material remaining on the wafer can cause defects in the fabricated ICs. Such removal is performed carefully to avoid chemically modifying or physically damaging the wafer. Although existing resist removal techniques have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.